1. Field of the Invention
This invention relates generally to a computer or larger system which includes a processor capable of a low power mode and which is capable of exiting the low power mode upon receipt of an external input.
2. Background of Related Art
Many computers such as personal computers (PCs) include a game port interface for interfacing, e.g., with a joystick.
For instance, FIG. 2 is a block diagram depicting a conventional joystick device 400 interfaced with a conventional game port interface 450. The game port interface 450 is accessed by other devices in a larger system using a bus such as an Industry Standard Architecture (ISA) Bus 480.
The game port interface 450 conventionally includes a timer such as a 558 quad timer 460, and interface logic and appropriate tri-state buffering to form a bus interface, e.g., ISA interface 470.
The conventional joystick is comprised basically of two variable resistors, one in an x-axis direction and the other in a y-axis direction. Each of the variable resistors change resistance as the joystick changes position. Some joystick devices include more than one joystick. For example, a 4-axis joystick device 400 such as that shown in FIG. 1 includes two joysticks.
A conventional game port interface 450 is comprised basically of a capacitor in parallel with each variable resistor of the joystick device 400. Thus, respective timing constants T=RC are formed between each variable resistor and its respective capacitor in the game port interface 450. As each joystick in the joystick device 400 changes position, the timing constants formed by the parallel combination of the variable resistors and capacitors change.
The 558 quad timer 460 includes four timers within one package. All four timers in the 558 quad timer 460 may be used for the four variable resistors of the 4-axis joystick device 400. Alternatively, four 555 timers could be combined to form an equivalent timer element. Similarly, a 2-axis joystick device may use only two of four available timers in a 558 quad timer, or may use only two 555 timers.
FIG. 3 shows a timing diagram showing the operation of each of the timers in a game port interface.
In particular, as shown in waveform (a) of FIG. 3, each of the timers in the 558 quad timer 460 are triggered under normal operation by a fire enable signal 461, e.g., initiated by a host processor over the ISA bus 480 (FIG. 2). The fire enable signal 461 resets the respective timer and starts the measurement of the position of the joystick device 400 in the relevant axis.
Waveform (b) of FIG. 3 shows a resultant pulse or data signal 463 output by the 558 quad timer 460 enabled or triggered by the fire enable signal 461 shown in waveform (a). The length 488 of the data signal 463 corresponds to the RC time constant resulting from the present value of the variable resistance in the relevant axis of the joystick device 400 and the value of the capacitor in parallel with that variable resistance. Thus, as FIG. 3 shows, the width of the data signal 463 represents the position of the joystick in the relevant axis.
FIG. 4 is a more detailed diagram of a conventional game port interface 450 in a computer such as a personal computer (PC).
In particular, the conventional game port interface 450 includes the 558 or similar quad timer 460, with capacitors 622-628 associated respectively with four input lines corresponding to 4 axes of the joystick device 400. Series resistors 632-638 prevent a short circuit condition across an input to the 558 quad timer 460. The joystick device 400 shown in FIG. 4 includes four axes of motion, i.e., two joysticks, and two buttons associated with each of the two joysticks.
The conventional game port interface 450 further includes a bus interface 470 such as an ISA bus interface. The ISA bus interface 470 includes an address decoder 662 and a data latch 664. The address decoder 662 provides appropriate fire enable signals 661 to the 558 quad timer 460, and an enable signal 665 to the data latch 664. Resistors 602-608 prevent floating inputs to the data latch 664 when the joystick device 400 is not connected to the game port interface 450, and capacitors 612-618 provide a filtering mechanism to, e.g., prevent spikes in signals to the data latch 664.
To conserve power (e.g., battery power), computers or other processor systems (particularly laptop computers and the like) enter a power down mode after a period of non-use. Conventional game port interfaces, which are typically triggered by the computer or processor system, thus cannot conventionally detect movement of a joystick while the computer or processor system is in a low power or power down mode. Conventionally, an external device such as a Universal Asynchronous Receiver Transmitter (UART) must communicate with the processor 601 to draw the processor 601 out of the power down mode. However, this requires action by a user other than through the joystick 400, wasting time and increasing the required activity of the user.
For instance, a processor 601 as shown in FIG. 4 accesses and polls the joystick device 400 via the ISA bus 480 during normal operation by causing a fire enable signal 661 to trigger the 558 quad timer 460. However, while the processor 601 is in a power down mode the 558 quad timer 460 does not receive the fire enable signal 661.
There is thus a need for an interface and method which allows a joystick to wake up a processor from a low power or power down mode.